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Method Overriding :  Method of base class enhanced in derived class. Used that as virtual method. Concept of polymorphism Method Overloading :  Multiple method with same name but different signature. Different set of argument . virtual void print(int x);  virtual void print(bit y) This is not supported in System Verilog.

  Setup time:  Setup time is the minimum time the data must arrive before active edge of clock signal Hold time:   hold time is the minimum time the data cannot change after active edge of clock signal.

à A full case is a case statement in which all possible all possible case expression can be matched with case items or case default. à If it is possible to find binary expression that doesn't case item the case statement is not full. à A parallel case statement is a case statement in which it is possible to match a case expression with one and only one case item if it is possible to find a case expression that would match more than one case item the matching case is called overlapping or non parallel.