Does System Verilog support Method Overriding and Method Overloading.

Method Overriding : 

Method of base class enhanced in derived class. Used that as virtual method. Concept of polymorphism

Method Overloading : 

Multiple method with same name but different signature. Different set of argument .

virtual void print(int x); 
virtual void print(bit y)

This is not supported in System Verilog.